MetaWells PJ71MXX

Signal Chain ICs

PJ71M89

Datasheet

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Product Description

2:8 - I2C/I3C Intelligent Multiple Port Hub Devices

Product Features

Two Master Side (upstream/controller) Ports

Up to eight Slave Side (downstream/target) Ports

On-Chip I2C/I3C Slave (target) Interface

Master Side Port multiplexer

Master switching via in-band I2C/I3C commands or pin selection

Master-Master communication and messaging support

Hot Join support

Support both I2C and I3C Basic 1.0 Protocol

All ports support 1.0 to 1.8V I2C/I3C compatible operation

All ports support I2C Open-Drain only operation up to 3.3V

JEDEC SPD/Module Management Bus Context support

Master to Slave analog switch mode support

Support analog switch mode

Support re-driving mode

Mixed I2C/I3C Bus support

In-Band Interrupt (IBI) and IBI Optimization support

Single 3.3V power supply

Master-Slave Level shifting support

On-Chip Voltage Regulators or direct platform connection of IO supplies

SMBus transaction agent for SMBus compatibility

SMBus SCL stretching support

SMBus SCL stretching support in Open-Drain Only Operation

Network partition support

Support non-transparent bridging

Applications

Product Introduction

Product Specifications

Consultation List

Product Introduction

The PJ71M4x/8x is a family of I2C/I3C Multiple Port Hub devices featuring two I2C/I3C Master Side Ports and up to eight I2C/IC Slave Side Ports. A PJ71M89 device provides connectivity to up to two masters (Controllers), and up to eight slaves (Targets). By cascading and duplicating the PJ71M4x/8x, the user builds a PJ71M4x/8x Hub Network to provide connectivity to a number of devices, with extended reach distance, and running with different level of I2C, I3C, and SMBus protocols. In the PJ71M4x/8x device, each of Master Side Port is associated with an on-chip I2C/I3C slave interface. Each I2C/I3C interface accesses on-chip registers. Master-Master communication is achieved with shared registers and intra-port IBI channels. One of the two Master Side Ports is selected to connect to a 1:N Hub network, which allows the selected master to get access to the enabled Slave Side Ports in the Hub network. The master selection multiplexer allows the two masters to share the downstream I2C/I3C network. The 1:N I2C/I3C Hub network allows the management of the I2C/I3C hierarchy with expansion to up to eight Slave Side Ports. The expanded ports allow the system to reduce the load that the selected master sees at any moment. The Hub network maintains software level transparently. All devices connected to the Hub Slave Side Ports are accessed the same way as if all ports directly connected as if the Hub network does not exist. The Hub network also allows physical segmentation of the I2C/I3C hierarchy employing on the fly connecting and disconnecting to any of the expanded ports. Each Slave Side Port is associated with a Bus Agent. This Agent independently receives or transmits legacy SMBus transactions and allows SCL Stretching within the SMBus segment behind the Slave Side Port. When the SMBus Agent is active, the Agent is engaged directly with the Slave Side Port and the Hub Network to the port is disconnected.

Product Specifications

Recommended Operating Conditions

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Symbol

Parameter

Min

Typ

Max

Unit

VDDIN

Input Supply Voltage

1.7

3.3

3.6

VDD18

Logic Supply Voltage, Generated by LDO

1.7

1.8

1.9

VIO_1.0

IO Supply Voltage, LDO Output set to 1.0V

0.95

1.0

1.05

VIO_1.1

IO Supply Voltage, LDO Output set to 1.1V

1.05

1.1

1.15

VIO_1.2

IO Supply Voltage, LDO Output set to 1.2V

1.15

1.2

1.25

VIO_1.8

IO Supply Voltage, LDO Output set to 1.8V

1.7

1.8

1.9

Ambient Operation Temperature

-40

°C

Junction Operating Temperature

-40

125

°C

Key Electrical Characteristics

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Symbol

Parameter

Test Condition

Min

Max

Unit

IDD

VDDIN Current

VDDIN=3.3V, Controller/Target Ports in idle state

SW_RON

Analog Switch Path Resistance

DC level around 0.5V

CIO

IO pin Capacitance

100Mhz, DC = 0.5V

CSW

Analog Switch Path total Capacitance, including IO pin capacitance

100Mhz, DC = 0.5V, Master Side Port and Slave Side Port connected by Analog Switch

Zo_50

Driver Impedance at 50-ohm setting

DC voltage at 0.5*VIO Temperature Range: 0~85°C, nominal VIO

Zo_40

Driver Impedance at 40Ω setting

DC voltage 0.5*VIO Temperature Range: 0~85°C, nominal VIO

Zo_30

Driver Impedance at 30Ω setting

DC voltage 0.5*VIO Temperature Range: 0~85°C, nominal VIO

Zo_20

Driver Impedance at 20Ω setting

DC voltage 0.5*VIO Temperature Range: 0~85°C, nominal VIO

Rpu_2k_33

2kΩ Pull-up Resistor value to VDDIN 3.3V

REG#25, SSPzORTS_SDA_Pullup resistor setting = 2kΩ; REG#23, OD_Only bit is set

1.65

2.30

KΩ

Rpu_2k_18

2kΩ Pull-up Resistor value to VIO 1.8V

REG#25, SSPORTS_SDA_Pullup resistor setting = 2kΩ; REG#23, OD_Only bit is cleared

1.65

2.35

KΩ

Rpu_2k_10

2kΩ Pull-up Resistor value to VIO 1.0V

REG#25, SSPORTS_SDA_Pullup resistor setting = 2kΩ; REG#23, OD_Only bit is cleared

1.60

2.20

KΩ

Rpu_1k_33

1kΩ Pull-up Resistor value to VDDIN 3.3V

REG#25, SSPORTS_SDA_Pullup resistor setting = 1kΩ; REG#23, OD_Only bit is set

0.93

1.35

KΩ

Rpu_1k_18

1kΩ Pull-up Resistor value to VIO 1.8V

REG#25, SSPORTS_SDA_Pullup resistor setting = 1kΩ; REG#23, OD_Only bit is cleared

0.88

1.35

KΩ

Rpu_1k_10

1kΩ Pull-up Resistor value to VIO 1.0V

REG#25, SSPORTS_SDA_Pullup resistor setting = 1kΩ; REG#23, OD_Only bit is cleared

0.84

1.20

KΩ

Rpu_500_33

500Ω Pull-up Resistor value to VDDIN 3.3V

REG#25, SSPORTS_SDA_Pullup resistor setting = 500Ω; REG#23, OD_Only bit is set

0.45

0.66

KΩ

Rpu_500_18

500Ω Pull-up Resistor value to VIO 1.8V

REG#25, SSPORTS_SDA_Pullup resistor setting = 500Ω; REG#23, OD_Only bit is cleared

0.44

0.66

KΩ

Rpu_500_10

500Ω Pull-up Resistor value to VIO 1.0V

REG#25, SSPORTS_SDA_Pullup resistor setting = 500Ω; REG#23, OD_Only bit is cleared

0.41

0.58

KΩ

Rpu_250_33

250Ω Pull-up Resistor value to VDDIN 3.3V

REG#25, SSPORTS_SDA_Pullup resistor setting = 250Ω; REG#23, OD_Only bit is set

0.23

0.33

KΩ

Rpu_250_18

250Ω Pull-up Resistor value to VIO 1.8V

REG#25, SSPORTS_SDA_Pullup resistor setting = 250Ω; REG#23, OD_Only bit is cleared

0.22

0.33

KΩ

Rpu_250_10

250Ω Pull-up Resistor value to VIO 1.0V

REG#25, SSPORTS_SDA_Pullup resistor setting = 250Ω; REG#23, OD_Only bit is cleared

0.22

0.33

KΩ

VILM_OD

Input low voltage Master Side Ports in OD_Only Mode

DC swipe, OD Only Operation

-0.3

0.5

VIHM_OD

Input high voltage Master Side Ports in OD_Only Mode

DC swipe, OD Only Operation

0.7

3.6

VILM

Input low voltage Master Side Ports in OD/PP compatible Mode

DC swipe

-0.3

0.35VIO

VIHM

Input high voltage Master Side Ports in OD/PP compatible Mode

DC swipe

0.65*VIO

VIO+0.3

VILS_OD

Input low voltage Slave Side Ports in OD_Only Mode

DC swipe, OD Only Operation

-0.3

0.6

VIHS_OD

Input high voltage Slave Side Ports in OD_Only Mode

DC swipe, OD Only Operation

0.85

VDDIIN+0. 3

VILS

Input low voltage Slave Side Ports in OD/PP compatible Mode

DC swipe, Push/Pull Operation, GPIO, Bus Agent Mode

-0.3

0.35*VIOS

VIHS

Input high voltage Slave Side Ports in OD/PP compatible Mode

DC swipe, Push/Pull Operation, GPIO, Bus Agent Mode

0.65*VIOS

VIOS+0.3

RDRV_EXT

Slave Side Port external slave device’s pull down driver impedance

Measure at VILS Level.

100

CLOAD

Slave Side Port maximum Capacitive Load

Lumped capacitance, including the capacitance of the PCB trace and device pin capacitance

200

VIL_MSEL

Input low voltage of MSEL pin

DC swipe

-0.3

0.3

VIH_MSEL

Input high voltage of MSEL pin

DC swipe

0.75

3.6

ILMSEL[5]

MSEL leakage current tolerance

Leakage current limit of keeping the MSEL as HiZ state

RDRV_MSEL

MSEL Pin driver resistance for static logic setting[6]

The resistance of IO driver (or tie high/tie-low resistor) drives MSEL pin to static logic high or logic low.

KΩ

VOL_ODL

Output low voltage I2C/I3C Ports

DC swipe, with 1K internal pull-up, VIO<1.5V

0.25

VOL_ODH

Output low voltage I2C/I3C Ports

DC swipe, with 1K internal pull-up, VIO>=1.5V

0.35

VOL_PP

Output low voltage I2C/I3C Ports

DC swipe, IIoad = 4mA

Zo*IIoad* 1.25

VOH_PP

Output high voltage I2C/I3C Ports

DC swipe, 4mA load, VIO=1.0V, 1.1V, 1.2V, 1.8V; Zo calibrated

VIO - Zo*Iload* 1.3

VIO_PG_Clr_Lo_10[9]

VIO Power Good Status Clear Low Threshold for 1.0V setting